enVention LLC is seeking candidates for an ASIC/FPGA design and verification engineer. Experience with SystemVerilog/UVM formal verification is a big plus.
Requirements:
BS, Electrical or Computer Science/Engineering
5+ years of experience in digital design for ASIC/FPGA devices. More senior candidates are also welcome to apply.
VHDL or Verilog hardware description language
Digital logic synthesis, simulation, and timing closure
Digital design tools (Xilinx, Cadence, Mentor, ModelSim, etc.)
Digital testbenches and formal verification with SystemVerilog/UVM
Ability to analyze electrical schematics
Strong oral and written technical communication
Ability to create and maintain good documentation
Writing and automating regression tests
Ability to work in a secured environment
US citizen
Ability to obtain and maintain a US security clearance